Abstract: It is possible for ferroelectric negative capacitance transistor to make the sub-threshold swing lower than the theoretical limit of 60 mV/dec, which is the key to break through the bottleneck of reducing working voltage VDD and device size in the future. Since the concept of low power consumption negative capacitance transistor was proposed in 2008, this kind of transistor has been attracting numerous attention from researchers thanks to its simple device structure and excellent circuit performance. Nevertheless, the weakness of the transistor that based on ferroelectric materials with negative capacitance characteristics are becoming increasingly prominent, particularly, the instability of negative capacitance. It must be a serious block for the application of the transistor. Compared with conventional transistors, negative capacitance transistors exhibit two great advantages when applied to low-power circuits. First, the sub-threshold slope can be lower than 60 mV/dec, and there will be no decline in switching current ratio and no increase in static leakage current while the circuit operating voltage is reduced. Second, the device size can be smaller which contribute to the reduction of circuit area. However, due to the hysteresis characteristic of ferroelectric materials, the negative capacitance transistor show serious hysteresis in switching circuit, leading to the disorder of logic circuit and abnormal working situation. Besides, the complexity of the cause of negative capacitance makes it quite difficult to be modeled. Hence, in recent 10 years, in addition to studying the effects of ferroelectric material and its parameters on device performance, the researchers have also put great efforts in sorting out the key factors that dominate the hysteresis phenomenon, and proposed several effective methods to suppress hysteresis phenomenon. At present, hysteresis window can approach to zero through adjusting the proportion of negative capacitance and transistor capacitance. The mathematical model of negative capacitance, which was in good agreement with the experimental results, did not appear until 2017. Whereas, there is no scientific measuring method for the parameters in the model, and further researches and explorations are still needed. The fabrication process of negative capacitance transistor is simple, and compatible with standard CMOS process. After the completion of baseline MOSFET, ferroelectric material with negative capacitance characteristics are deposited on the top of the gate to form a cascade gate. The difficulty of preparing negative capacitor transistors lies in stabilizing the interface between ferroelectric and oxide and reducing the defects and vacancies. Currently, negative capacitance transistors, whose minimum subthreshold slope of the final product can reach as low as 16 mV/dec, have been successful fabricated in laboratory both at home and abroad. However, it suffers from extremely high occurence probability of hysteresis, and more research is needed to improve the fatigue ability, stability and reliability of the devices. Ferroelectric materials that are commonly used in negative capacitance transistor include PbZrTiO3 (PZT), SrBi2Ta2O9 (SBT), P(VDF-TrFE), hafnium-based oxides. Among them, haf-nium-based oxides are recognized as suitable materials for practical production and application because of their environmental friendliness, small size, and excellent performance. In this article, the working principle of ferroelectric negative capacitance transistor is discussed, the physical mechanism and experimental test method of negative capacitance characteristics are analyzed, the latest progress in negative capacitance transistor(NCFET) made by worldwide institutions is introduced. Finally, the future development direction of NCFET in device structure, material selection and device reliability is proposed.
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2019, Vol. 33 
