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材料导报  2024, Vol. 38 Issue (9): 22110004-7    https://doi.org/10.11896/cldb.22110004
  无机非金属及其复合材料 |
环栅晶体管制备中SiGe选择性刻蚀技术综述
刘恩序1,2, 李俊杰1,2,*, 刘阳1, 杨超然1,2, 周娜1,2, 李俊峰1,2, 罗军1,2, 王文武1,2
1 中国科学院微电子研究所,北京 100029
2 中国科学院大学集成电路学院,北京 100049
An Overview of SiGe Selective Etching Technology Used for the Preparation of Gate-All-Around Transistor
LIU Enxu1,2, LI Junjie1,2,*, LIU Yang1, YANG Chaoran1,2, ZHOU Na1,2, LI Junfeng1,2, LUO Jun1,2, WANG Wenwu1,2
1 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
2 School of Integrated Circuits, University of the Chinese Academy of Sciences, Beijing 100049, China
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摘要 环栅(Gate-all-around,GAA)晶体管是3 nm以下节点替代现有鳍式晶体管(FinFET)最有竞争力的器件结构,能有效改善器件尺寸不断微缩带来的短沟道效应。与FinFET相比,GAA器件制备的工艺流程中内侧墙制备和沟道释放是新引入的工艺模块,均需要SiGe选择性刻蚀技术。工艺要求SiGe作为牺牲层被选择性刻蚀去除,且尽可能减少对Si沟道的损伤。本文对环栅晶体管制备工艺中所需的SiGe选择性刻蚀技术进行了综述,主要分析了器件结构的发展趋势及SiGe选择性刻蚀的应用,并分类综述了常规SiGe选择性刻蚀方法以及新型选择性刻蚀技术的发展历程,分析了各种技术的优点和不足。最后对SiGe选择性刻蚀技术面临的挑战进行了分析,并对其未来可能的发展趋势进行了展望。
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刘恩序
李俊杰
刘阳
杨超然
周娜
李俊峰
罗军
王文武
关键词:  锗硅  选择性刻蚀  环栅  内侧墙  沟道释放  纳米线  纳米片    
Abstract: Gate-all-around (GAA) transistors are the most competitive device structure to replace existing fin field effect transistors(FinFET) below the sub-3 nm node, effectively improve the short-channel effect caused by the continuous shrinking of device size along Moore's Law. In the process flow of GAA device preparation, inner spacer preparation and channel release are newly introduced process modules relative to FinFET, and both require SiGe selective etching technology. SiGe is required to be removed as a sacrificial layer by selective etching with as little damage as possible to the Si channel. This paper presents a review of the SiGe selective etching techniques required in the gate-all-around (GAA) transistor fabrication process. Firstly, we analyze the development trend of device structure and the application of SiGe selective etching. Secondly, the development of conventional SiGe selective etching methods and new selective etching techniques are categorized and reviewed. After that the advantages and shortcomings of each technique are summarized. Finally, this study analyzes the challenges faced by SiGe selective etching technology, and prospects the possible future development trends.
Key words:  SiGe    selective etching    gate-all-around    inner spacer    channel release    nanosheet    nanowire
出版日期:  2024-05-10      发布日期:  2024-05-13
ZTFLH:  TN305.7  
基金资助: 中国科学院先导A项目(XDA0330300);中国科学院支撑技术人才项目(E2YR01X001)
通讯作者:  * 李俊杰,中国科学院微电子研究所先导工艺研发中心高级工程师、硕士研究生导师。2004年武汉理工大学材料科学专业本科毕业,2007年北京航空航天大学信息功能材料专业毕业后在北方华创工作历任资深刻蚀工艺工程师及产品经理,2013年到中国科学院微电子研究先导工艺研发中心工作,2021年获得中国科学院大学微电子与固体电子学博士学位,入选中国科学院人才项目。主要从事先导刻蚀工艺及纳米器件研究,申请发明专利250余项,发表论文90余篇。lijunjie@ime.ac.cn   
作者简介:  刘恩序,2021年6月于吉林大学获得理学学士学位。现为中国科学院大学微电子研究所硕士研究生,在王文武研究员和李俊杰高级工程师的指导下进行研究。目前主要从事GAA器件的工艺研究。
引用本文:    
刘恩序, 李俊杰, 刘阳, 杨超然, 周娜, 李俊峰, 罗军, 王文武. 环栅晶体管制备中SiGe选择性刻蚀技术综述[J]. 材料导报, 2024, 38(9): 22110004-7.
LIU Enxu, LI Junjie, LIU Yang, YANG Chaoran, ZHOU Na, LI Junfeng, LUO Jun, WANG Wenwu. An Overview of SiGe Selective Etching Technology Used for the Preparation of Gate-All-Around Transistor. Materials Reports, 2024, 38(9): 22110004-7.
链接本文:  
https://www.mater-rep.com/CN/10.11896/cldb.22110004  或          https://www.mater-rep.com/CN/Y2024/V38/I9/22110004
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